Receive Operation - NEC UPD98413 User Manual

Figure 4-8. Back-to-back Cell Transmission (Status Polling)
TXCLK
TXADDR[1:0]
PORT0 PORT1 PORT2
TXCLAV0
PORT0
TXENB_B
TXDATA[31:0]
P12 X
TXPRTY X
TXSOC
X : Invalid

4.2.4 Receive operation

The µPD98413 supports both the direct status indication mode and the status-polling mode (Multi-PHY operation
with 1 RXCLAV).
(1) Direct status indication
The µPD98413 implements a dedicated RXCLAV signal for each of the ports. RXCLAV0 corresponds to the
port0, while RXCLAV3 corresponds to the port3.
The ATM device controls the flow of data from the µPD98413 on a per cell basis. The µPD98413 indicates
receive cell available information to the ATM device. The ATM device can select a port for transfer of a cell when
the port has indicated to the ATM device that it has at least one cell available. The µPD98413 deasserts the
RXCLAV0-3 coincident with RXSOC to indicate that the corresponding port of the µPD98413 has no subsequent
cell available. Once the RXCLAV0-3 has been asserted, it will have to stay asserted until the RXSOC is asserted
on that particular port.
A valid RXADDR[1:0] during the clock cycle before asserting the RXENB_B signal will select the port which will
transfer the next cell across the ATM interface. The µPD98413 decodes this signal and the specified port will be
ready to transfer cell data two clock cycles after RXENB_B goes low. The ATM device must deassert RXENB_B
two cycles before the end of the cell transfer, unless a back-to-back transfer is intended. The decode-response
timing between the RXENB_B and the RXDATA[31:0] is therefore two clock cycles
122
CHAPTER 4 INTERFACES
PORT3 PORT1
X
H1 P1 P7 P8
Figure 4-9. Receive Timing (Direct Status Indication)
PRELIMINARY
PORT1
P9 P10 P11 P12 H1
X
P1 P2 P3 P4
.
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