NEC UPD98413 User Manual page 116

(1) Transmit interface
The transmit interface uses the signals defined below.
TXCLK (input):
Transmit clock.
TXCLK is used to clock the transmit control signals and data. TXCLK cycles at a rate
up to 104MHz.
TXDATA[31:0] Transmit data.
(input):
TXDATA[31:0] is 32-bit data bus for the transmit data, from the ATM device to the
µPD98413. TXDATA31 is the MSB, TXDATA0 is the LSB.
TXSOC (input): Transmit start of cell.
TXSOC is an active high signal asserted by the ATM device to indicate the start of cell
position. TXSOC is only asserted during the first clock cycle of the data transfer.
TXENB_B (input):
Transmit enable.
TXENB_B is an active low signal and the assertion is coincident with the start of the
cell transfer. TXENB_B is used for address selection during the last clock cycle
before it is asserted.
TXPRTY (input):
Transmit data path parity.
TXPRTY is served as the odd or even parity over TXDATA[31:0].
TXCLAV0-3 Transmit cell buffer available.
(output):
TXCLAV is used to indicate that space for at least one cell is available in the
µPD98413 transmit FIFO.
TXCLAV0-3 are used in the direct status indication mode.
corresponds to the port0, TXCLAV3 corresponds to the port3.
TXADDR[1:0] Transmit address.
(input):
TXADDR[1:0] is used to select the port for which the transmit data is to be
destined. The address is used in both the direct status indication mode and the
status-polling mode. The following addresses show the corresponding ports.
116
CHAPTER 4 INTERFACES
0: port0, 1: port1, 2: port2, 3: port3
PRELIMINARY
TXCLAV0 is used in the status-polling mode.
Then TXCLAV0
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