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(2) Receive interface
The receive interface uses the signals defined below.
RXCLK (input):
Receive clock.
RXCLK is used to clock the receive control signals and data. RXCLK cycles at a rate
up to 104MHz.
RXDATA[31:0]
Receive data.
RXDATA[31:0] is 32-bit data bus for the receive data, from the µPD98413 to the ATM
(output):
device. RXDATA31 is the MSB, RXDATA0 is the LSB.
RXSOC (output):
Receive start of cell.
RXSOC is an active high signal asserted by the µPD98413 to indicate the start of cell
position. RXSOC is only asserted during the first clock cycle of the data transfer.
RXENB_B
Receive enable.
(input):
RXENB_B is an active low signal asserted by the ATM device to initiate a cell transfer.
RXENB_B is used for address selection during the last clock cycle before it is
asserted.
RXPRTY (output):
Receive data path parity.
RXPRTY serves as the odd or even parity over RXDATA.
RXCLAV0-3
Receive cell available.
RXCLAV is used to indicate that at least one cell is available in the µPD98413
(input):
receive FIFO. RXCLAV0 is used in the status-polling mode. RXCLAV0-3 are
used in the direct status indication mode. Then RXCLAV0 corresponds to the
port0, RXCLAV3 corresponds to the port3.
RXADDR[1:0]
Receive address.
(input):
RXADDR is used to select the port from which the receive data is to be read.
The address is used in both the direct status indication mode and the status
polling mode. The following addresses show the corresponding ports.
CHAPTER 4 INTERFACES
0: port0, 1: port1, 2: port2, 3: port3
PRELIMINARY
NEC confidential and Proprietary
117
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