Interrupt - NEC UPD98413 User Manual

4.8.3 Interrupt

If an event occurs, such as line defect or alarm detection or performance counter overflow, µPD98413 activates
the interrupt signal (INT_B) to notify the host of the event.
The interrupt signals for all four ports are multiplexed and output as a single INT_B pin. The port causing the
interrupt signal to be output is indicated in the INT register.
(1) Interrupt register, Interrupt causes register and detailed cause register
A register that identifies the cause of an interrupt consists of 6 separate registers: the interrupt register (INT),
interrupt cause register and detailed cause register. The interrupt signal is activated if any of the INT register bits
is set to 1. The bits of the INT register are set when even one of the bits of the corresponding Interrupt cause
register is set to 1. The bits of the GEV, ICT and ICR register are set when even one of the bits of the
corresponding detailed cause register at the lower stage is set to 1. When the host detects that an interrupt
signal has been asserted active, it first reads the INT register, second reads the GEV, ICT and ICR registers and
then reads the detailed cause register corresponding to the bit of the GEV, ICT and ICR registers that has been
set, to identify the event that has occurred.
The bits of the GEV, ICT and ICR registers are only ORed with the bits of the detailed cause register. They are
not latched. If a detailed cause register is cleared to all 0 by reading (or writing), the corresponding bit of the
GEV, ICT and ICR register is also cleared to 0.
The GEV, ICT and ICR register and detailed cause register has a mask register. The bit arrangement of this
mask register is the same as that of the corresponding cause register, so that each event can be masked or
unmasked. Even if a masked bit of the INT register is set to 1, INT_B is not asserted active. Even if a masked
bit of a detailed cause register is set to 1, it is not reflected on the GEV, ICT and ICR registers. Even when
masked, the bits of the GEV, ICT and ICR registers and detailed cause register are set or reset depending on the
detection status of an alarm or fault. In the default mode, all the causes are masked.
CHAPTER 4 INTERFACES
Figure 4-27. Interrupt Signal
µ
PD98413
INT
Port 0
register
Port 1
Port 2
Port 3
PRELIMINARY
INT_B
Management
entity
NEC confidential and Proprietary
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