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6.5 TAP Controller Operation
The TAP controller operates as follows.
The state of the controller is changed by either of (1) and (2) below.
(1) Rising edge of JCK pin signal
(2) JRST_B pin input
The TAP controller generates signals that control the operations of the bypass register, boundary scan register, and
instruction register defined by the IEEE1149.1 JTAG Boundary Scan Standard (see Figures 6-4 and 6-5).
The JDO pin output buffer and the peripheral circuit that selects a register whose contents are to be output to the
JDO pin are controlled as shown in Table 6-1. The JDO pin defined in this table changes at the falling edge of the
JCK pin signal after it has entered each state.
Controller State
Test-Logic-Reset
Undefined
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Instruction register
Exit1-IR
Undefined
Pause-IR
Exit2-IR
Update-IR
Capture-DR
Shift-DR
Data register (boundary scan register, bypass register)
Exit1-DR
Undefined
Pause-DR
Exit2-DR
Update-DR
CHAPTER 6 JTAG BOUNDARY SCAN
Table 6-1. Operation in Each Controller State
Selected Register to Be Driven to JDO Pin
PRELIMINARY
JDO Pin Driver
High impedance
Active
High impedance
Active
High impedance
NEC confidential and Proprietary
313
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