Buffer Memory Address Comparison - Mitsubishi Electric MELSEC-A/QnA Series Handbook

6
HIGH-SPEED COUNTER MODULE REPLACEMENT

6.3.4 Buffer memory address comparison

Sequence program change is required as the assignment of buffer memory differs.
For details of the buffer memory or sequence program, refer to the High-Speed Counter Module User's
Manual.
AD61S1
Address
(Dec.)
CH1 CH2
1 33 Preset value write (Lower and middle)
(2) (34) Preset value write (Upper)
3 35 Mode register
4 36 Present value read (Lower and middle)
(5) (37) Present value read (Upper)
6 38 Set value read/write (Lower and middle)
(7) (39) Set value read/write (Upper)
Address in parentheses in the above table indicates the upper 8 bits
of 24-bit data.
Name Read/write
W
R/W
R
R/W
QD62-H02
Address
(Dec.) Name
CH1 CH2
0 32
Preset value setting
1 33
2 34
Present value
3 35
4 36
Coincidence output point set No.1
5 37
6 38
Coincidence output point set No.2
7 39
8 40 Overflow detection flag
9 41 Counter function selection setting
10 42 Sampling/periodic setting
11 43 Sampling/periodic counter flag
12 44
Latch count value
13 45
14 46
Sampling count value
15 47
16 48 Periodic pulse count previous
17 49 value
18 50
Periodic pulse count present value
19 51
20 52
Ring counter minimum value
21 53
22 54
Ring counter maximum value
23 55
24 56
to to System area (Not used)
31 63
Read/write
(L)
R/W
(H)
(L)
R
(H)
(L)
(H)
R/W
(L)
(H)
R
R/W
(L)
(H)
(L)
(H) R
(L)
(H)
(L)
(H)
(L)
(H)
R/W
(L)
(H)
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