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DDCSWR—DDC Switch Register
7
Bit
:
—
Initial value
:
0
R/W
:
R/(W)*
1008
6
5
—
—
0
0
1
1
R/(W)*
R/(W)*
Reserved bit
IIC clear 3 to 0
CLR3 CLR2 CLR1 CLR0
0
1
Note: 1. Should always be written with 0.
2. Always read as 1.
H'FDB5
4
3
—
CLR3
0
1
1
1
2
R/(W)*
W*
0
—
—
1
0
0
1
1
0
1
—
—
—
2
1
CLR2
CLR1
1
1
2
2
W*
W*
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latch cleared
Invalid setting
IIC
0
CLR0
1
2
W*
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