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Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV
Description
0
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: This bit is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a
normal SCI, 0 should be written in this bit.
Bit 0
SMIF
Description
0
Operates as normal SCI (smart card interface function disabled)
1
Smart card interface function enabled
16.2.10 IrDA Control Register (IrCR)
Bit
:
Initial value :
R/W
:
R/W
IrCR is an 8-bit read/write register that selects the SCI0 function.
IrCR is initialized to H'00 when in hardware standby mode.
Bit 7—IrDA enable (IrE): Sets SCI0 input and output for normal SCI operation or IrDA
operation.
Bit 7
IrE
Description
0
TxD0/IrTxD and RxD0/IrRxD pins operate as TxD0 and RxD0.
1
TxD0/IrTxD and RxD0/IrRxD pins operate as IrTxD and IrRxD.
612
7
6
IrE
IrCKS2
IrCKS1
0
0
R/W
5
4
IrCKS0
0
0
R/W
R/W
3
2
—
—
0
0
—
—
(Initial value)
(Initial value)
1
0
—
—
0
0
—
—
(Initial value)
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