Hitachi H8S/2633 Hardware Manual page 208

(1) Operation Timing for Burst Access (High-Speed Page Mode)

Figure 7-22 shows the operation timing for burst access. When the DRAM space is successively

accessed, the CAS signal and column address output cycle (2 state) are continued as long as the

row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0

bits of the MCR specify which row address is compared.

Note: n=2 to 5

OE* is enabled when OES=1.

Figure 7-22 Operating Timing in High-Speed Page Mode

The bus cycle can also be extended in burst access by inserting wait states. The method and timing

of inserting the wait states is the same as in full access. For details, see Section 7.5.8, "Wait