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8.1.5
Register Configuration
Table 8-3 summarizes the DMAC registers.
Table 8-3
DMAC Registers
Channel Name
0
Memory address register 0A
I/O address register 0A
Transfer count register 0A
Memory address register 0B
I/O address register 0B
Transfer count register 0B
1
Memory address register 1A
I/O address register 1A
Transfer count register 1A
Memory address register 1B
I/O address register 1B
Transfer count register 1B
0, 1
DMA write enable register
DMA terminal control register DMATCR
DMA control register 0A
DMA control register 0B
DMA control register 1A
DMA control register 1B
DMA band control register
Module stop control register A MSTPCRA
Note: * Lower 16 bits of the address.
212
Abbreviation R/W
MAR0A
R/W
IOAR0A
R/W
ETCR0A
R/W
MAR0B
R/W
IOAR0B
R/W
ETCR0B
R/W
MAR1A
R/W
IOAR1A
R/W
ETCR1A
R/W
MAR1B
R/W
IOAR1B
R/W
ETCR1B
R/W
DMAWER
R/W
R/W
DMACR0A
R/W
DMACR0B
R/W
DMACR1A
R/W
DMACR1B
R/W
DMABCR
R/W
R/W
Initial
Value
Address* Bus Width
Undefined H'FEE0
Undefined H'FEE4
Undefined H'FEE6
Undefined H'FEE8
Undefined H'FEEC
Undefined H'FEEE
Undefined H'FEF0
Undefined H'FEF4
Undefined H'FEF6
Undefined H'FEF8
Undefined H'FEFC
Undefined H'FEFE
H'00
H'FF60
H'00
H'FF61
H'00
H'FF62
H'00
H'FF63
H'00
H'FF64
H'00
H'FF65
H'0000
H'FF66
H'3F
H'FDE8
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
8 bits
8 bits
16 bits
16 bits
16 bits
16 bits
16 bits
8 bits
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