Hitachi H8S/2633 Hardware Manual page 563

13.6.3 Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is disabled even if a compare match event occurs.
Figure 13-12 shows this operation.
ø
Address
Internal write signal
TCNT
TCOR
Compare match signal
Figure 13-12 Contention between TCOR Write and Compare Match
542
TCOR write cycle by CPU
T1
TCOR address
N
N
T2
N+1
M
TCOR write data
Disabled