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Hitachi H8S/2633 Hardware Manual page 759

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SDA
Bit 0
SCL
8
Internal clock
BBSY bit
Master receive mode
Figure 18-18 Points for Attention Concerning Reading of Master Receive Data
• Notes on Start Condition Issuance for Retransmission
Figure 18-19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart.
A
9
ICDR reading
prohibited
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Stop condition
(a)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
Start condition
issuance
741

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