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DADRAH0—PWM (D/A) Data Register AH0
DADRAL0—PWM (D/A) Data Register AL0
DADRBH0—PWM (D/A) Data Register BH0
DADRBL0—PWM (D/A) Data Register BL0
DADRAH1—PWM (D/A) Data Register AH1
DADRAL1—PWM (D/A) Data Register AL1
DADRBH1—PWM (D/A) Data Register BH1
DADRBL1—PWM (D/A) Data Register BL1
15
14
Bit (CPU)
:
Bit (Data)
:
13
12
DA13
DA12
DADRA
1
1
Initial value
:
R/W
R/W
R/W
:
DADRB
:
DA13
DA12
Initial value
:
1
1
R/W
:
R/W
R/W
1010
DADRH
13
12
11
10
9
11
10
9
8
7
DA11
DA10
DA9
DA8
DA7
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
D/A data 13 to 0
DA11
DA10
DA9
DA8
DA7
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
D/A data 13 to 0
H'FDB8
H'FDB9
H'FDBA
H'FDBB
H'FDBC
H'FDBD
H'FDBE
H'FDBF
DADRL
8
7
6
5
4
6
5
4
3
2
DA6
DA5
DA4
DA3
DA2
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Carrier frequency select
0 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD
1 Basic cycle = resolution (T) ×256. DADR range = H'0103 to H'FFFF
DA6
DA5
DA4
DA3
DA2
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Carrier frequency select
0 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD
1 Basic cycle = resolution (T) × 256. DADR range = H'0103 to H'FFFF
3
2
1
0
1
0
—
—
DA1
DA0
CFS
—
1
1
1
1
R/W
R/W
R/W
—
DA1
DA0
CFS
REGS
1
1
1
1
R/W
R/W
R/W
R/W
Register select
0 DADRA and DADRB access enabled.
1 DACR and DACNT access enabled.
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
PWM1
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