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23.1.2
Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23-1 shows the register
configuration.
Table 23-1 Clock Pulse Generator Register
Name
System clock control register
Low-power control register
Note:* Lower 16 bits of the address.
23.2
Register Descriptions
23.2.1
System Clock Control Register (SCKCR)
Bit
:
PSTOP
Initial value
:
R/W
:
R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
High-Speed Mode,
Bit 7
Medium-Speed Mode,
PSTOP
Sub-Active Mode
0
ø output (initial value)
1
Fixed high
Bits 6 and 4—Reserved: These bits are always read as 0 and cannot be modified.
842
Abbreviation
SCKCR
LPWRCR
7
6
—
0
0
—
Sleep Mode
Sub-Sleep Mode
ø output
Fixed high
R/W
R/W
R/W
5
4
—
—
STCS
0
0
—
—
R/W
Description
Software
Standby Mode,
Watch Mode
Fixed high
Fixed high
Initial Value
H'00
H'00
3
2
SCK2
SCK1
0
0
R/W
R/W
Hardware
Standby Mode
High impedance
High impedance
Address*
H'FDE6
H'FDEC
1
0
SCK0
0
0
R/W
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