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13.3.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer
mode) or compare matches of the 8-bit timer channel 0 could be counted by the timer of channel 1
(compare match counter mode). In this case, the timer operates as below.
16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions
as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the
lower 8 bits.
• Setting of compare match flags
The CMF flag in TCSR0 and TCSR2 is set to 1 when a 16-bit compare match event occurs.
The CMF flag in TCSR1 and TCSR3 is set to 1 when a lower 8-bit compare match event
occurs.
• Counter clear specification
If the CCLR1 and CCLR0 bits in TCR0 (TCR2) have been set for counter clear at compare
match, the 16-bit counter (TCNT0 and TCNT1 (TCNT2 and TCNT3) together) is cleared
when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1
(TCNT2 and TCNT3) together) is cleared even if counter clear by the TMRI01 (TMRI23)
pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR1 and TCR3 are ignored. The lower 8
bits cannot be cleared independently.
• Pin output
Control of output from the TMO0 (TMO2) pin by bits OS3 to OS0 in TCSR0 (TCSR2) is
in accordance with the 16-bit compare match conditions.
Control of output from the TMO1 (TMO3) pin by bits OS3 to OS0 in TCSR1 (TCSR3) is
in accordance with the lower 8-bit compare match conditions.
Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 (TCR3) are B'100, TCNT1
(TCNT3) counts compare match A's for channel 0 (channel 2).
Channels 0 to 3 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Note on Usage: If the 16-bit counter mode and compare match counter mode are set
simultaneously, the input clock pulses for TCNT0 and TCNT1 (TCNT2 and TCNT3) are not
generated and thus the counters will stop operating. Software should therefore avoid using both
these modes.
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