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DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ
pin is selected to 1.
Figure 8-32 shows an example of DREQ pin low level activated single address mode transfer.
ø
DREQ
Address bus
DACK
DMA control
Idle
Channel
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
[1]
edge of ø, and the request is held.
[2] [5]
The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6]
The DMAC cycle is started.
[4] [7]
Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8-32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Bus release
DMA single
Transfer source/
destination
Single
Request clear
Request
period
Minimum of
2 cycles
[1]
[2]
[3]
Acceptance resumes
Bus release
Idle
Single
Request
Minimum of
2 cycles
[4]
[5]
[6]
Bus
DMA single
release
Transfer source/
destination
Idle
Request clear
period
[7]
Acceptance resumes
281
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