• Module stop mode can be set
The initial setting enables DMAC registers to be accessed. DMAC operation is halted by
setting module stop mode
8.1.2
Block Diagram
A block diagram of the DMAC is shown in figure 8-1.
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Legend
DMAWER
: DMA write enable register
DMATCR
: DMA terminal control register
DMABCR
: DMA band control register (for all channels)
DMACR
: DMA control register
MAR
: Memory address register
IOAR
: I/O address register
ETCR
: Executive transfer counter register
208
Control logic
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer
Figure 8-1 Block Diagram of DMAC
Internal address bus
Address buffer
Internal data bus
Processor
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B