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Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
Bit 4
TEE0
Description
TEND0 pin output disabled
0
TEND0 pin output enabled
1
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,
regardless of the transfer source. An exception is block transfer mode, in which the transfer end
signal indicates the transfer cycle in which the block counter reached 0.
Bits 3 to 0—Reserved: These bits are always read as 0 and cannot be modified.
8.4.3
Module Stop Control Register (MSTPCR)
Bit
:
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
R/W
MSTPCRA is a 8-bit readable/writable register that performs module stop mode control.
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 24.5, Module Stop
Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a
manual reset and in software standby mode.
Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode.
Bits 7
MSTPA7
Description
0
DMAC module stop mode cleared
1
DMAC module stop mode set
7
6
0
0
R/W
R/W
5
4
1
1
R/W
R/W
3
2
1
1
R/W
R/W
(Initial value)
1
0
1
1
R/W
(Initial value)
239
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