Hitachi H8S/2633 Hardware Manual page 437

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.

When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both

edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is

ignored and the phase counting mode setting has priority.

Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is

ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected.

Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT

counter clock. The clock source can be selected independently for each channel. Table 11-4 shows

the clock sources that can be set for each channel.

Table 11-4 TPU Clock Sources

Blank : No setting

Count at rising edge

Count at falling edge

Count at both edges

Internal Clock

ø/16 ø/64 ø/256 ø/1024 ø/4096

External Clock

TCLKA TCLKB TCLKC TCLKD Channel

(Initial value)