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13.6
Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer.
13.6.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 13-10 shows this operation.
ø
Address
Internal write signal
Counter clear signal
TCNT
Figure 13-10 Contention between TCNT Write and Clear
540
TCNT write cycle by CPU
T1
T2
TCNT address
N
H'00
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