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24.2.2
System Clock Control Register (SCKCR)
Bit
:
PSTOP
Initial value
:
R/W
:
SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls ø output. See Section 24.12, ø Clock Output Disabling Function for details.
High-Speed Mode,
Bit 7
Medium-Speed Mode,
PSTOP
Sub-Active Mode
0
ø output (initial value)
1
Fixed high
Bits 6 and 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
Description
0
Specified multiplication factor is valid after transition to software standby mode, watch
mode, or subactive mode
1
Specified multiplication factor is valid immediately after STC bits are rewritten
860
7
6
—
0
0
R/W
—
Sleep Mode,
Sub-Sleep Mode
ø output
Fixed high
5
4
—
—
STCS
0
0
—
—
R/W
Description
Software Standby
Mode, Watch Mode
Fixed high
Fixed high
3
2
SCK2
SCK1
0
0
R/W
R/W
Hardware Standby
Mode
High impedance
High impedance
1
0
SCK0
0
0
R/W
(Initial value)
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