Hitachi H8S/2633 Hardware Manual page 560

Sample Application

In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle,

as shown in figure 13-9. The control bits are set as follows:

[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is

cleared when its value matches the constant in TCORA.

[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA

compare match and to 0 at a TCORB compare match.

With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with

a pulse width determined by TCORB. No software intervention is required.

Figure 13-9 Example of Pulse Output

Counter clear