Hitachi H8S/2633 Hardware Manual page 309

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 8-13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 8-35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
ø
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A Request clear
Channel 0B
Channel 1
Bus
release
284
DMA read DMA write
Write Idle
Request Selection
hold
Request
Non-
selection
hold
Channel 0A
transfer release
Figure 8-35 Example of Multi-Channel Transfer
DMA read DMA write
Read Write
Request clear
Request
Selection
hold
Bus Channel 0B
transfer
DMA read
Idle Read Write
Request clear
Channel 1 transfer
Bus
release
DMA
DMA write read
Read