Hitachi H8S/2633 Hardware Manual page 322

9.1.3 Register Configuration
Table 9-1 summarizes the DTC registers.
Table 9-1 DTC Registers
Name
DTC mode register A
DTC mode register B
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
DTC enable registers
DTC vector register
Module stop control register
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, do not clear the RAME
bit in SYSCR to 0.
Abbreviation R/W
MRA —*
MRB —*
SAR —*
DAR —*
CRA —*
CRB —*
DTCER R/W
DTVECR R/W
MSTPCRA R/W
Initial Value
2
Undefined
2
Undefined
2
Undefined
2
Undefined
2
Undefined
2
Undefined
H'00
H'00
H'3F
1
Address*
3
—*
3
—*
3
—*
3
—*
3
—*
3
—*
H'FE16 to H'FE1E
H'FE1F
H'FDE8
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