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5.2.2
Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)
Bit
:
Initial value
:
R/W
:
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5-3
Correspondence between Interrupt Sources and IPR Settings
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
IPRL
IPRO
7
6
—
IPR6
IPR5
0
1
—
R/W
R/W
6 to 4
IRQ0
IRQ2
IRQ3
IRQ6
IRQ7
Watchdog timer 0
PC break
TPU channel 0
TPU channel 2
TPU channel 4
8-bit timer channel 0
DMAC
SCI channel 1
8-bit timer 2, 3
SCI channel 3
5
4
IPR4
—
1
1
R/W
—
3
2
IPR2
IPR1
0
1
R/W
R/W
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
Refresh timer
A/D converter, watchdog timer 1
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1
SCI channel 0
SCI channel 2
IIC (Option)
SCI channel 4
1
0
IPR0
1
1
R/W
95
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