Hitachi H8S/2633 Hardware Manual page 159

Block Diagram

Figure 7-1 shows a block diagram of the bus controller.

External bus control signals

External DRAM

control signal

ABWCR : Bus width control register

DRAM controller

: Access state control register

: Bus control register H

: Bus control register L

: Wait control register H

: Wait control register L

Figure 7-1 Block Diagram of Bus Controller

Area decoder

: Memory control register

: DRAM control register

: Refresh timer counter

: Refresh time constand register

Internal control

Bus mode signal

CPU bus request signal

DTC bus request signal

DMAC bus request signal

CPU bus acknowledge signal

DTC bus acknowledge signal

DMAC bus acknowledge signal