Hitachi H8S/2633 Hardware Manual page 925

2
Table 25-10 I C Bus Timing
Conditions: V = PLV
CC
maximum operating frequency, T
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse
elimination time
SDA input bus free time
Start condition input hold time
Retransmission start condition input
setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Note: * 17.5t can be set according to the clock selected for use by the I
cyc
see section 18.4, Usage Notes.
912
= 3.0 V to 3.6 V, PV
CC
Symbol
t
SCL
t
SCLH
t
SCLL
t
Sr
t
Sf
t
SP
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
C
b
= 3.0 V to 5.5 V, V
CC
= –20°C to +75°C
a
Ratings
Min Typ
12t —
cyc
3t —
cyc
5t —
cyc
— —
— —
— —
5t —
cyc
3t —
cyc
3t —
cyc
3t —
cyc
0.5t —
cyc
0 —
— —
= 0 V, ø = 5 MHz to
SS
Max Unit Notes
— ns Figure 25-33
— ns
— ns
7.5t * ns
cyc
300 ns
1t ns
cyc
— ns
— ns
— ns
— ns
— ns
— ns
400 pF
2
C module. For details,