Hitachi H8S/2633 Hardware Manual page 445

Bit 7 Bit 6 Bit 5 Bit 4
Channel IOB3 IOB2 IOB1 IOB0 Description
1 0 0
1
1 0
1
Bit 7 Bit 6 Bit 5 Bit 4
Channel IOB3 IOB2 IOB1 IOB0 Description
2 0 0
1
1
*
422
0 0 TGR1B is Output disabled
output
1
compare
0
1
register
1
0 0
1
1 0
1
0 0 TGR1B is
input
1
capture
*
1
register
* *
0 0 TGR2B is Output disabled
output
1
compare
0
1
register
1
0 0
1
1 0
1
0 0 TGR2B is
input
1
capture
*
1
register
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCB1 pin
Input capture at both edges
Capture input Input capture at generation of
source is TGR0C TGR0C compare match/input
compare match/ capture
input capture
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCB2 pin
Input capture at both edges
(Initial value)
*: Don't care
(Initial value)
*: Don't care