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11.2.4
Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit
:
TTGE
Initial value :
R/W
:
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
:
TTGE
Initial value :
R/W
:
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
432
7
6
—
0
1
—
7
6
—
TCIEU
0
1
—
R/W
5
4
—
TCIEV
TGIED
0
0
—
R/W
5
4
TCIEV
0
0
R/W
3
2
TGIEC
0
0
R/W
R/W
3
2
—
—
0
0
—
—
1
0
TGIEB
TGIEA
0
0
R/W
R/W
1
0
TGIEB
TGIEA
0
0
R/W
R/W
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