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12.3.5 Inverted Pulse Output ........................................................................................... 516
12.3.6 Pulse Output Triggered by Input Capture............................................................. 517
12.4 Usage Notes ...................................................................................................................... 518
Section 13 8-Bit Timers (TMR)
13.1 Overview............................................................................................................................ 521
13.1.1 Features ................................................................................................................. 521
13.1.2 Block Diagram...................................................................................................... 522
13.1.3 Pin Configuration.................................................................................................. 523
13.1.4 Register Configuration.......................................................................................... 524
13.2 Register Descriptions ......................................................................................................... 525
13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).......................................................... 525
13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3) ............................... 525
13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)................................ 526
13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3) ................................................. 526
13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3).................................. 529
13.2.6 Module Stop Control Register A (MSTPCRA).................................................... 532
13.3 Operation............................................................................................................................ 533
13.3.1 TCNT Incrementation Timing.............................................................................. 533
13.3.2 Compare Match Timing........................................................................................ 534
13.3.3 Timing of External RESET on TCNT .................................................................. 536
13.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 536
13.3.5 Operation with Cascaded Connection .................................................................. 537
13.4 Interrupts ............................................................................................................................ 538
13.4.1 Interrupt Sources and DTC Activation ................................................................. 538
13.4.2 A/D Converter Activation..................................................................................... 538
13.5 Sample Application............................................................................................................ 539
13.6 Usage Notes ....................................................................................................................... 540
13.6.1 Contention between TCNT Write and Clear ........................................................ 540
13.6.2 Contention between TCNT Write and Increment................................................. 541
13.6.3 Contention between TCOR Write and Compare Match ....................................... 542
13.6.4 Contention between Compare Matches A and B.................................................. 543
13.6.5 Switching of Internal Clocks and TCNT Operation ............................................ 543
13.6.6 Interrupts and Module Stop Mode........................................................................ 545
Section 14 14-Bit PWM D/A
14.1 Overview............................................................................................................................ 547
14.1.1 Features ................................................................................................................. 547
14.1.2 Block Diagram...................................................................................................... 548
14.1.3 Pin Configuration.................................................................................................. 549
14.1.4 Register Configuration.......................................................................................... 549
14.2 Register Descriptions ......................................................................................................... 550
14.2.1 PWM D/A Counter (DACNT).............................................................................. 550
x
....................................................................................... 521
............................................................................................ 547
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