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Port E Data Register (PEDR)
Bit
:
PE7DR
Initial value :
R/W
:
R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).
PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port E Register (PORTE)
Bit
:
PE7
Initial value :
R/W
:
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin
states, as PEDDR and PEDR are initialized. PORTE retains its prior state by a manual reset or in
software standby mode.
7
6
PE6DR
PE5DR
0
0
R/W
7
6
PE6
—*
—*
R
R
5
4
PE4DR
PE3DR
0
0
R/W
R/W
5
4
PE5
PE4
—*
—*
R
R
3
2
PE2DR
PE1DR
0
0
R/W
R/W
3
2
PE3
PE2
—*
—*
R
R
1
0
PE0DR
0
0
R/W
R/W
1
0
PE1
PE0
—*
—*
R
R
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