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Hitachi H8S/2633 Hardware Manual page 763

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19.1.2
Block Diagram
Figure 19-1 shows a block diagram of the A/D converter.
AVCC
Vref
10-bit D/A
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ADTRG
ADCR
: A/D control register
ADCSR
: A/D control/status register
ADDRA
: A/D data register A
ADDRB
: A/D data register B
ADDRC
: A/D data register C
ADDRD
: A/D data register D
746
+
Comparator
Sample-and-
hold circuit
Figure 19-1 Block Diagram of A/D Converter
Module data bus
A
A
A
A
D
D
D
D
D
D
D
D
R
R
R
R
A
B
C
D
Control circuit
Internal data bus
A
A
D
D
C
C
S
R
R
ø/2
ø/4
ø/8
ø/16
ADI
interrupt
Conversion start
trigger from 8-bit
timer or TPU

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