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Table 14-4 Settings and Operation (Examples when ø = 10 MHz)
Resolution
CKS
T (µs)
CFS
0
0.1
0
1
1
0.2
0
1
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.
Base
Conversion
Cycle (µs)
Cycle (µs)
6.4
1638.4
25.6
1638.4
12.8
3276.8
51.2
3276.8
T
(if OS = 0)
L
T
(if OS = 1)
H
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
Fixed DADR Bits
Bit Data
Precision
(Bits)
3 2 1 0
14
12
0 0 409.6
10
0 0 0 0 102.4
14
12
0 0 409.6
10
0 0 0 0 102.4
14
12
0 0 819.2
10
0 0 0 0 204.8
14
12
0 0 819.2
10
0 0 0 0 204.8
Conversion
Cycle* (µs)
1638.4
1638.4
3276.8
3276.8
559
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