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(4) Notes
The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example,
if the 2nd of successive reads of different areas is a DRAM access, only the T
not the T
cycle. Figure 7-36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are
1
valid in burst access in RAS down mode, and an idle cycle is inserted. Figure 7-37 (a) and (b)
shows the timing.
Address bus
Data bus
Figure 7-36 Example of DRAM Access after External Read
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
Figure 7-37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1=1)
External read
T
1
ø
RD
DRAM space read
T
T
T
p
r
c1
DRAM space read
T
T
T
2
3
p
External read
T
T
T
c2
1
1
cycle is inserted,
P
T
T
T
r
c1
c2
DRAM space read
T
T
T
2
3
c1
Idle cycle
T
T
c1
c2
197
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