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Bit 4
DTE0A
Description
0
Data transfer disabled
1
Data transfer enabled
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an
interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Bit 3—Data Transfer End Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B
transfer end interrupt.
Bit 3
DTIE1B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A
transfer end interrupt.
Bit 2
DTIE1A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
Bit 1—Data Transfer End Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B
transfer end interrupt.
Bit 1
DTIE0B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A
transfer end interrupt.
224
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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