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2.6
Instruction Set
2.6.1
Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2-1.
Table 2-1
Instruction Classification
Function
Data transfer
Arithmetic
operations
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer EEPMOV
Notes: B-byte size; W-word size; L-longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Not available in the H8S/2633 Series.
38
Instructions
MOV
1
1
POP*
, PUSH*
LDM, STM
3
MOVFPE*
, MOVTPE*
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS
MAC, LDMAC, STMAC, CLRMAC
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc*
, JMP, BSR, JSR, RTS
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
3
Size
Types
BWL
5
WL
L
B
BWL
23
B
BWL
L
BW
WL
B
—
BWL
4
8
B
14
—
5
9
—
1
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