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Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the
DMAC single address transfer bus timing.
Bit 3
DDS
Description
0
When performing DMAC single address transfers to DRAM, always execute full
access. The DACK signal is output as a low-level signal from the T
1
Burst access is also possible when performing DMAC single address
tranfers to DRAM. The DACK signal is output as a low-level signal
from the T
Bit 2—Read CAS Timing Select (RCTS): Selects the CAS signal output timing.
Bit 2
RCTS
Description
CAS signal output timing is same when reading and writing.
0
When reading, CAS signal is asserted half cycle earlier than when writing.
1
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write
buffer function in the external write cycle or the DMAC single address cycle.
Bit 1
WDBE
Description
0
Write data buffer function not used
1
Write data buffer function used
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
0
Wait input by WAIT pin enabled
1
or T
cycle.
C1
2
or T
cycle.
r
1
(Initial value)
(Initial value)
(Initial value)
(Initial value)
145
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