Hitachi H8S/2633 Hardware Manual page 297

DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the

DREQ pin is selected to 1.

Figure 8-23 shows an example of DREQ pin falling edge activated normal mode transfer.

Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising

edge of ø, and the request is held.

The request is cleared at the next bus break, and activation is started in the DMAC.

Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.

When the DREQ pin high level has been sampled, acceptance is resumed after the

write cycle is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 8-23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin

high level sampling has been completed by the time the DMA write cycle ends, acceptance

resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and

this operation is repeated until the transfer ends.

Request clear period

Minimum of 2 cycles

Request clear period

Minimum of 2 cycles

Acceptance resumes

Acceptance resumes