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• External request
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
(6) Block transfer mode
In response to a single transfer request, a block transfer of the specified block size is carried
out. This is repeated the specified number of times, once each time there is a transfer request.
At the end of each single block transfer, one address is restored to its original setting. An
interrupt request can be sent to the CPU or DTC when the specified number of block transfers
have been completed. Both addresses are specified as 24 bits.
8.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8-6 summarizes register functions in sequential mode.
Table 8-6
Register Functions in Sequential Mode
Register
23
MAR
23
15
H'FF
IOAR
15
ETCR
Legend
MAR
: Memory address register
IOAR : I/O address register
ETCR : Transfer count register
DTDIR : Data transfer direction bit
242
Function
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source
Destination
address
address
register
register
0
Destination
Source
address
address
register
register
0
Transfer counter
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Incremented/
decremented every
transfer
Fixed
transfer; transfer
ends when count
reaches H'0000
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