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10.13.2 Register Configuration
Table 10-22 shows the port G register configuration.
Table 10-22 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Notes: 1. Indicates the low order 16 bits of the address
2. Value of bits 4 to 0
3. The initial value varies according to the mode.
Port G Data Direction Register (PGDDR)
Bit
:
Modes 4 and 5
Initial value
:
Undefined
R/W
:
Modes 6 and 7
Initial value
:
Undefined
R/W
:
PGDDR is an 8-bit write only register and specifies I/O of each pin of port G in bit units. Read
processing is invalid. Bits 7 to 5 are reserved bits. When the contents are read, undefined values
are read.
In modes 4 and 5, the PG4DDR bits are initialized to H'10 (bit 4 to 0) in power-on reset or
hardware standby mode, in modes 6 and 7, the bits are initialized to H'00 (bit 4 to 0). In manual
reset or software standby mode, PGDDR retains the last status. Use the OPE bit of SBYCR to
select whether the bus control output pin retains the output state or becomes the high-impedance
when the mode is changed to a software standby mode.
• Modes 4 to 6
When PGDDR is set to 1, pins PG4 to PG1 function as bus control signal output pins (CS0 to
CS3, OE). When PGDDR is cleared to 0, the pins function as input ports.
When the DRAM interface is set, pin PG0 functions as the CAS output pin. When PGDDR is
set to 1, the pin functions as an output port. When PGDDR is cleared to 0, the pin functions as
an input port.
398
7
6
—
—
Undefined
Undefined
—
—
Undefined
Undefined
—
—
Abbreviation
PGDDR
PGDR
PORTG
5
4
—
PG4DDR
PG3DDR
1
—
W
0
—
W
R/W
Initial Value*
W
H'10/H'00*
RW
H'00
R
Undefined
3
2
PG2DDR
PG1DDR
0
0
W
W
0
0
W
W
2
1
Address*
3
H'FE3F
H'FF0F
H'FFBF
1
0
PG0DDR
0
0
W
W
0
0
W
W
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