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5.1.3
Pin Configuration.................................................................................................. 93
5.1.4
Register Configuration.......................................................................................... 93
5.2
Register Descriptions ......................................................................................................... 94
5.2.1
System Control Register (SYSCR)....................................................................... 94
5.2.2
Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................. 95
5.2.3
IRQ Enable Register (IER) ................................................................................... 96
5.2.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97
5.2.5
IRQ Status Register (ISR) .................................................................................... 98
5.3
Interrupt Sources................................................................................................................ 99
5.3.1
External Interrupts ................................................................................................ 99
5.3.2
Internal Interrupts.................................................................................................. 100
5.3.3
Interrupt Exception Handling Vector Table ......................................................... 100
5.4
Interrupt Operation............................................................................................................. 105
5.4.1
Interrupt Control Modes and Interrupt Operation ................................................ 105
5.4.2
Interrupt Control Mode 0...................................................................................... 108
5.4.3
Interrupt Control Mode 2...................................................................................... 110
5.4.4
Interrupt Exception Handling Sequence ............................................................... 112
5.4.5
Interrupt Response Times ..................................................................................... 113
5.5
Usage Notes ....................................................................................................................... 114
5.5.1
Contention between Interrupt Generation and Disabling ..................................... 114
5.5.2
Instructions that Disable Interrupts....................................................................... 115
5.5.3
Times when Interrupts are Disabled .................................................................... 115
5.5.4
Interrupts during Execution of EEPMOV Instruction .......................................... 116
5.6
DTC and DMAC Activation by Interrupt.......................................................................... 116
5.6.1
Overview............................................................................................................... 116
5.6.2
Block Diagram...................................................................................................... 116
5.6.3
Operation .............................................................................................................. 117
Section 6
PC Break Controller (PBC)
6.1
Overview............................................................................................................................ 119
6.1.1
Features ................................................................................................................. 119
6.1.2
Block Diagram...................................................................................................... 120
6.1.3
Register Configuration.......................................................................................... 121
6.2
Register Descriptions ......................................................................................................... 121
6.2.1
Break Address Register A (BARA)...................................................................... 121
6.2.2
Break Address Register B (BARB) ...................................................................... 122
6.2.3
Break Control Register A (BCRA) ....................................................................... 122
6.2.4
Break Control Register B (BCRB) ....................................................................... 124
6.2.5
Module Stop Control Register C (MSTPCRC) .................................................... 124
6.3
Operation............................................................................................................................ 125
6.3.1
PC Break Interrupt Due to Instruction Fetch........................................................ 125
6.3.2
PC Break Interrupt Due to Data Access ............................................................... 125
6.3.3
Notes on PC Break Interrupt Handling................................................................. 126
.......................................................................... 119
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