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Reference Frequency Divider
The external 75 kHz crystal oscillation frequency is divided to generate the following ten types of PLL reference
frequency signals; 1 kHz, 1.39 kHz, 1.56 kHz, 2.78 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz and 25 kHz
respectively. These signals can be selected by the reference port data.
The selected signal is supplied as a reference frequency for the phase comparator as described below. The PLL on/off is
controlled by the contents of the reference port.
1. Reference Port
This is an internal port for selecting ten types of reference frequency signals. This port is located in data port 6 as selected
at the select port, and can be accessed by using the OUT1 instruction with [CN = 5H] specified in the operand. When the
reference port is set to all "1", all the programmable counters, IF counters, reference counters and the phase comparator will
be stopped and enter the PLL off mode. When the reference port setting is set, the frequency division setting data for the
programmable counter will be updated. Therefore, the frequency division number of the programmable counter must be
determined before setting the reference port.
Y1
Y2
φL15(E)
R0
R1
Reference frequency select code
Note:
After a system reset, this port is set to all "1" and becomes to PLL off mode.
Note:
When the ΙΝΗ pin input permission is set by using the ΙΝΗ ENA bit, the PLL off mode becomes the
ΙΝΗ input or the PLL off mode as shown above.
Y4
Y8
R2
R3
102
R3
R2
R1
R0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
1
3
0
0
1
0
4
0
1
0
1
5
0
1
0
0
6
0
1
1
1
7
0
1
1
0
8
1
0
0
1
0
0
1
9
0
A
1
0
1
1
0
1
1
B
1
1
0
0
C
1
D
1
1
0
1
1
1
0
E
1
1
1
1
F
TC9349AFG
Oscillation
frequency
1 kHz
1.3889 kHz
1.5625 kHz
2.7778 kHz
3 kHz
3.125 kHz
5 kHz
6.25 kHz
12.5 kHz
25 kHz
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PLL off mode
2006-02-24
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