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The pulse counter measures the number of pulses of the input of PCTR in the (P3-3) pin.
The POS and NEG bits specify the input pin clock edge from the rising edge, the falling edges and both edges. This bit is
fixed in the normal operation.
The DOWN bit sets the up or down of the 8-bit counter. When this bit is set to "0", the up count operation becomes
active. When this bit is set to "1", the down count operation becomes active. Up and down counts can be switched freely.
If the clock edge is inputted during execution of the switch instruction, this count will be cancelled, please remain aware
of this.
The OVER F/F bit is set to "1" when an edge of 2
this OVER F/F bit is detected to add or subtract the number of times of overflow on the data memory. After detection is
carried out by this bit, set the OVER RESET bit to "1" to reset OVER F/F.
The CTR RESET bit resets the 8-bit counter only. The counter will be reset each time this bit is set to "1".
Counter data is loaded into the data memory in binary format.
Pulse counter control and data loading are accessed by the OUT2/IN2 instruction with [CN = BH~DH] specified in the
operand.
2. Pulse Counter Circuit Configuration
OVER RESET
CTR RESET
F/F
OVER F/F
3. Example of Pulse Counter Timing
RESET execution
RESET 実行
パルスカウンタ制御ビット
Data set to pulse
へのデータセット
counter control bit
DOWNビット
DOWN bit
CTR in入力
CTR in input
カウンタデータ
Counter data
OVER F/F
OVER F/F
Note: The CTRin input pin is the Schumitt input.
Note: The pulse counter uses the CPU operation clock (75 kHz of low-speed clock) to determine the sampling
and edges. Input a pulse width of at least twice the CPU operation clock.
Note: When the pulse counter function is used and the I/O port input is enabled to break, the wait or clock stop
instruction will be released due to changes in serial input. Note that this requires input setting from the
I/O port control and reading of the I/O port input before execution of the instruction. he first pulse is not
counted. When the clock stop is released, CPU execution will be started after 100 ms of standby.
Note: When the pulse counter function is used, I/O port 3 can be set to the pull-up/pull-down state.
8
DOWN
8-bit up/down counters
8 bit up/down counter
PC0 ～ PC7
CTR /OVER
CTR/OVER
パルス幅最小30us 75kHz CPU動作時
Pulse width 30 us (minimum) (in 75 kHz CPU operation)
01H
02H
03H
or higher is inputted. To activate a count operation of 8 bits or more,
POS
NEG
CPU operation
clock
Edge Detection
Selector
Selector
Edge Detection
OVER
OVER
RESET 実行
RESET execution
（
）
FFH
00H
01H
88
TC9349AFG
Input enable
～
signal
40
P3-3/PCTRin
～
DOWNビット
Set DOWN bit "1"
"1"をセット
02H
N
N+1
N-1
N-2
2006-02-24
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