Toshiba TC9349AFG Manual page 36

(2) HARD WAIT mode
The operations of all elements, with the exception of the crystal resonator and doubler operating (V
can be suspended by execution of a WAIT instruction in which [P = 1H] has been specified in the operand. This
enables even greater levels of current consumption reduction than SOFT WAIT mode. This suspends the CPU
operation.
During hard wait mode, the state of the output port is maintained and all LCD output pins are fixed at the "L" level.
The wait status is assumed whenever the WAIT instruction is executed. Wait mode is canceled on the following
conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) If the V power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the
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VDD power supply break is enabled (BRAEK ENA bit (φL11(F)) = "1").
Note: Wait mode is also released when the V
the on state (at approximately 0.5 V or more) when the V
(BRAEK ENA bit ( φ L11(F)) = "1").
Note: The PLL OFF status will be assumed during wait mode.
Note: During wait mode, the power supply doubler circuit (V
the LCD (V
3. Backup mode by hardware
The backup mode by hardware detects the power supply voltage level of a V
There are two types of backup function by hardware: a decreased voltage detection function and a power supply off
detection function.
(1) Decreased voltage detection function
The decreased voltage detection function detects the V
prevents incorrect operation of the CPU. If the V
(V = 0.85V - 1.225V) potential when the detected decrease voltage function is enabled, CPU operation will be
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suspended; and if the V
functions continue to operate normally.
Decreased voltage detection operation is performed at intervals. The frequency of detection can be selected through
programming, with detection being performed at a rate of once every two instructions or 16 instruction cycles. Select
according to power consumption and speed of power supply variation.
The detection voltage can be set to an interval of 25 mV within the range of V
according to the specification. Since suspension of CPU operation can be prohibited, it is also possible to detect
residual battery level between 0.85 V and 1.225 V by varying the detection setting voltage and detecting the detection
flag. In this case, execute a backup instruction after detection of the minimum voltage level to prevent incorrect
operation of the CPU.
Where interrupt is permitted, the interrupt will be issued if the VSTOP F/F bit is set to "1". If interrupt is received,
the program will branch to 0003H address.
Moreover, PLL off-mode can be actuated during decreased voltage detection. Therefore the PLL can be quickly
suspended should the voltage drop.
The VSTOP F/F bit enables detection of suspension or of a fall below the detection voltage. Upon detection this bit
is set to "1" and will be reset by execution of flag reset (STOP F/F Reset = "1").
Through programming, therefore, it is possible to make various operation settings for when a decrease in the V
potential (battery voltage) occurs.
Note: Both serial interface and timer port are used for the interrupt function of the decreased voltage
detection circuit. When this interrupt is used, the interrupt function of the serial interface and the
timer port cannot be used.
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pin) and the doubler circuit for the LCD ( V
EE
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pin again rises above the set voltage, the CPU will restart. Although the CPU stops, other
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power supply pin in wait mode is changed from the off to
power supply break has been enabled
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pin), the constant-voltage supply circuit for
DB
pin) continue to operate.
LCD
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pin level, suspends the operation of the CPU and
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pin level falls below the decreased voltage detection setting
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TC9349AFG
/ V pin),
DB LCD
pin and actuates backup mode.
= 0.85 V ∼ 1.225 V. Set
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2006-02-24