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2. Data register (φL/K1C ~ φL/K1F), DAL address register (φL/K11(0) ~ φL/K11(3)) and
control bit
The data register is 16-bit register for which the program memory data is loaded when the DAL instruction and DALR
instruction are executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of
the OUT1/IN1 instructions for which [CN = CH ~ FH] has been specified in the operand. This register can be used for
loading LCD segment decoding operations, radio band edge data and data related to binary-to-BCD conversion.
The data register has a four-level interrupt stack register. On the issuing of interrupt, the 16 data register bits are
evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
φL/K10(6)
*/0
*/0
φL/K10(C)
φL/K10(F)
Page 0
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processing execution
LSB
φL/K1C
φL/K1D
φL/K1E
φL/K1F
Y1
ISRd0 ISRd1 ISRd2 ISRd3
ISRd4 ISRd5 ISRd6 ISRd7
0
1
ISRd1
ISRd1
ISRd1
ISRd1
2
3
4
5
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Page 3
At the time of RNI
instruction execution
Data register data (16 bits)
Data register data( 16 bit)
Y1
Y2
Y4
Y8
ｄ0
ｄ4
ｄ8
ｄ9
ｄ10
ｄ11
ｄ12
ｄ13
ｄ14
ｄ15
MSB
DALR instruction
／DAL instruction
/DAL instruction
execution
execution
Program memory
16 bit data
16-bit data
Program memory area
(ROM)
43
DAL address register (AR)
φL/K11
AR0
(0)
AR4
(1)
AR8
(2)
MVAR instruction
(3)
execution
Data select
（ φL/K1A）
DALR instruction indirect
specification address
Note: Whenever it executes a DALR instruction,
Note: Each time a DALR instruction is executed, the
+1 increment of the DAL address register
(AR) is done.
DAL address register (AR) is incremented by +1.
DAL instruction indirect
specification address
（ADDR3,r）
(ADDR3,r)
TC9349AFG
AR1
AR2
AR3
AR5
AR6
AR7
AR9
AR10 AR11
AR12 AR13
TROM
0
2006-02-24
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