Toshiba TC9349AFG Manual page 6

PIN No. Symbol Pin Name
6 C3
7 C4
Doubler output pin for
LCD driver
8 VLCD
Constant-voltage output
9 VEE
10 VCPU CPU power supply pin
P6-0/ADin1
(BRK9)
11~14
/AD analog input
P6-3/ADin4
(BRK12)
Function and Operation
Doubler output pin for the LCD driver.
The VLCD pin doubles the VEE pin
voltage to 3 V using the voltage doubler
capacitance between C3 and C4.
The doubled VLCD voltage is supplied to
the I/O port, the power supply of the LCD
driver, and the electronic volume power
supply.
Usually, the stabilizing capacitor (0.1 µF
typ.) is connected between the VLCD pin
and GND. The voltage doubler capacitor
(0.1 µF typ.) is connected between C3 and
C4.
Note: During reset or execution of a clock
stop instruction, the VLCD pin is set
to the VCPU power supply level.
Constant-voltage output pin.
The VEE pin outputs 1.5 V (typ.)
constant-voltage power supply.
The VEE potential is used for the voltage
doubler for the CPU, the clamp function of
the DC/DC converter and the reference
voltage of the A/D converter.
pin
The stabilizing capacitor (0.47 µF typ.) is
connected to the VEE pin.
Note: During reset or execution of the
clock stop instruction, the VEE pin
is at high impedance.
CPU power supply pin.
Normally, 1.2 to 3.6 V is applied. When
memory backup is required, VDB potential
is applied to this pin and this pin's potential
is held.
In backup state (at execution of the
CKSTP instruction), current dissipation
drops (0.5 µA or less), and the power
supply voltage can be reduced to 0.75 V.
If voltage is applied to this pin, the device
system is reset and the program starts
from address "0" (power-on reset).
Note: To operate the power-on reset, the
power supply should start up in 10
to 100 ms.
Note: To be used with VCPU ≤ VLCD.
4-bit N-ch open-drain I/O ports, allowing
input and output to be programmed in 1-bit
units.
If the ports are set as the input state of an
I/O port, these can be set to break pins.
The backup mode can be released by
changing the input state of the break pin in
the backup mode.
I/O ports are N-ch open-drain output. Up to
the V voltage can be applied to the AD
DB
I/O port 6 input pins.
Pins P6-0 to P6-3 can also be used for
analog input to the built-in 6-bit, 4-channel
A/D converter.
The conversion time of the built-in A/D
converter using the successive
comparison method is 240 µs.
The necessary pin can be programmed to
A/D analog input in 1-bit units.
Up to the doubled voltage VDB (VDD × 2)
can be input as the A/D input voltage.
6
TC9349AFG
Remarks
⎯
⎯
V
LCD
V
EE
V
CPU
To A/D
converter
V
DD
Input instruction
Release enables
2006-02-24