Toshiba TC9349AFG Manual page 28

System Reset
The device system will be reset when the RESET pin is subject to the "L" level or when a voltage of 0 V → 1.2 V to
3.6 V is supplied to the V
after a standby time of 100 ms following the startup of the low-speed oscillator. Since the power-on reset function is being
used, the RESET terminal should be fixed at "H" level under normal conditions.
Note: The input circuit of the RESET pin operates on a V
V~V .
CPU
Note: The power-on reset circuit operates on power startup of the V
Note: The LCD common output and the segment output will be fixed at "L" level during system reset and during
the subsequent standby period.
Note: It is necessary to initialize any internal port shown in the above-mentioned I/O map that has not been
initialized after system reset. The
reset, while the
φL2D
After system reset, this port is set to "1".
V DD pin
V pin
CPU
pin
RESET
X pin
OUT
Standby
(about 100 ms)
Reset
Internal reset
signal
Note: If the V power supply voltage falls below 0.9 V or the V
DD
to clock stop mode and operate the reset function. The V
power supply is restarted (power-on reset).
Note: V pins are usually supplied from doubler voltage V
CPU
pin (power-on reset). On system reset, the program will start from "0" address immediately
CPU
mark on the I/O map shows a port or bit that is set to "0" after system
mark shows a port or bit that is set to "1". No mark shows a port or bit that is unfixed.
φL2F
I/O
OUT2
Y1 Y2
MUTE control
8 IMUTE
POL
After system reset, these ports are set to "0"
(Note)
CPU
operation
< Timing of Operation >
power supply, and the input voltage level is 0
CPU
power supply.
CPU
Y4 Y8
After system reset, unmarked
port is unfixed.
MUTE
Break
ENA
(Note)
Standby
CPU
(about
operation
100 ms)
power supply voltage falls below 1.2 V, set
CPU
power supply voltage will be reset when the
CPU
pins. Refer to the backup mode item.
DB
28
TC9349AFG
GND
GND
GND
A crystal oscillator stops
during the reset from a reset pin.
CPU operation
Standby
(about 100 ms)
2006-02-24