Toshiba TC9349AFG Manual page 56

(2) Timer mode
Timer mode is a mode for detecting a regular time. Whenever the regular time is detected, an interrupt request is
executed and the counter reset. At this time, the control bit is set to 25 kHz or 1 kHz, the PW bit to "0", and the CR
bit to "0".
At this time, the timer coincidence data is
Timer time = IDn (coincidence data) × timer clock cycle
This sets the data for required timer interval.
Timer clock
Timer data IDn 00H
Coincidence pulse
(3) Pulse width measurement mode
Pulse width measurement mode enables the detection and measurement of the "H" or "L" pulse width of the
INTR1 input.
The control bit at this time is used to select 1 kHz or 25 kHz for the timer clock and set "1" to the PW bit. If the
PW bit is set to "1", the INTR1 input becomes the input enable signal of the counter clock and the timer clock is
input to the timer counter in the enabled state. Then, if the coincidence data values and counter values match, a timer
interrupt is issued.
The input logic is used in combination with the external interrupt logic setting (POS1/NEG1 bit).The timer counter
is "H" level if the POS1 bit and NEG1 bit are set to "1" and "0" respectively; and "L" level if the POS1 bit and
NEG1 bit are set to "0" and "1" respectively.
• Pulse width detection
The pulse width detection function detects a pulse width equal to or greater than a regular pulse width. This
function can be used for detection of the leader pulse of remote controls and data detection. At this time the control
bit is set to "0" for the GR Disable bit, and the timer counter is automatically reset on completion of pulse width
measurement. With automatic reset, no timer interrupt will be issued when the pulse width is below the set value.
Only on input of a pulse equal to or greater than the detection pulse width is a timer interrupt issued and detection
enabled. This feature enables the detection of data from remote control devices when used in combination with
external interrupts.
The detection pulse width at this time is as follows:
Detection pulse width = Idn (coincidence data) × the cycle of timer clock Idn ∞ 1(HEX)
• Measurement of pulse width
When the pulse width is being measured, the CR Disable bit of control bit is set to "1", setting to prohibited status
the execution of reset to the timer counter when pulse width measurement is finished. On completion of pulse width
measurement, the issuing of the external interrupt is detected, and the pulse width can be measured by referencing the
timer counter value. The pulse width at this time is as follows:
Pulse width = CTn (timer counter data) × the cycle of timer clock
After reading of the timer counter data (CR = "1"), the timer counter is reset and initialized.
25 kHz or 1 kHz
01H 02H 03H
56
IDn ≧ 1 (HEX)
IDn 00H 01H
ID
(N − 1)
Request for interrupt and
reset timer counter.
TC9349AFG
02H 03H
2006-02-24