Toshiba TC9349AFG Manual page 31

DC/DC converter for CPU
The device incorporates a DC/DC converter for the CPU power supply. The CPU doubler circuit comprises a charge
pump system utilizing a capacitor.
There is a built-in clamp control function, for which an electrical potential of 2.0, 2.5 and 3.0 V can be set through
programming.
The capacitor-utilizing charge pump system supplies a V
potential twice the V potential is output to the V
DD
following clamp setting using this method, the doubler potential also decreases.
Three types of 1/2 frequency can be selected for the doubler clock: 37.5 kHz, 75 kHz, and a high-speed oscillation clock.
After reset, a frequency of 37.5 kHz is output. Set the doubler clock to the required doubler capability.
The doubled V potential is supplied to the A/D converter and the V
DB
usually supplied to the V
CPU
Y1 Y2
φL14(8)
VC0 VC1
Note: If the OSC2 bit is set to "1", the doubler clock for the LCD driver is also changed simultaneously.
pin. Note that, if twice the voltage of the V
DB
pin through a Schottky diode.
Y4 Y8
CLAMP OSC2
Doubler clock frequency selection for doubler
OSC2 ON
OSC2
φL15(F)-Y2)
(
* 0
0 1
1 1 High-speed oscillator clock (300～600kHz)×1/2
Clamp function control
0: Off（V DD × 2）
1: On
Clamp voltage control
Note: This becomes effective only when the clamp function is ON.
VC0
VC1
0 0
0 1
1 0
1 1
31
level charge between the C1 and C2 pins, and a doubler
DD
constant-voltage circuit. The V
EE
Doubler Clock Frequency for the CPU
Low-speed oscillator clock (75kHz)×1/2
Low-speed oscillator clock (75kHz)
Clamp voltage
Prohibition
2.0V
2.5V
3.0V
TC9349AFG
pin decreases
DD
potential is
DB
Doubler Clock
Frequency for
the LCD Driver
Same as left
Low-speed
oscillator clock
2006-02-24