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Register port
The G-register, data register and DAL address register, which were mentioned in the description of the CPU, are arranged
on the I/O map, and treated as one of the internal ports. The carry flag can also be accessed from an I/O map. (Refer to the
section on I/O access of the stack register.)
Of these registers, the G-register, the carry flag, and the data register have a four-page interrupt stack register
corresponding to the four stack levels. On execution of interrupt processing, these contents are automatically stored in the
interrupt stack register together with the contents of data selection and automatically returned on execution of an RNI
instruction. (Refer to the section on the interrupt stack register.)
1. G-register (φL/K18, φL/K19)
This register addresses the row addresses (DR = 04H ~ 1FH) of the data memory during execution of the MVGD
instruction and MVGS instruction. The register is accessed with the OUT1/IN1 instruction for which [CN = 8H ~ 9H] has
been specified in the operand. Moreover, if the STGI instruction is used, data can be set to this register with a single
instruction.
This register has a four-level interrupt stack register. On the issuing of interrupt, the contents of the G-register are
evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are
executed and are ineffective when any other instruction is executed. Moreover, this register is unaffected
by the MVGD instruction and MVGS instruction.
Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 1FH in the G-
register (DR = 00H ~ 1FH).
Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRG0 ~ ISRG4
( φ L/K10(8), φ L/K10(9)) through programming.
φL/K10(6)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interruption stack pointer
Interrupt stack pointer
Interrupt stack pointer
Page
0
φL/K18
φL/K10(8)
ISRG0 ISRG1 ISRG2 ISRG3
1
2
3
Interrupt stack register
Interruption stack register
At the time of interrupt
At the time of interrupt
At the time of interruption
processing execution
processing execution
processing execution
Y1
Y2
Y4
Y8
G0
G1
G2
G3
G-register
STGI instruction
Ｉ0
Ｉ1
Ｉ2
Ｉ3
Ｉ*
42
φL/K10(9)
Page
ISRG4
*/0
*/0
0
1
2
3
At the time of RNI
instruction execution
Y1
Y2
Y4
φL/K19
G4
*
*
Specification of the low address of a data memory
G4
G3
0
0
0
0
0
0
Ｉ4
1
1
TC9349AFG
*/0
Y8
*
G2
G1
G0
DR
1
0
0
04H
1
0
1
05H
1
1
0
06H
1
1
1
1FH
2006-02-24
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